Requirements for lower electricity consumption and higher performance semiconductor devices has gradually increased. This has brought about continuous research and development to obtain high integration and high-speed operation of semiconductor devices. The continuously increasing integration is limited by the size of local interconnection wiring process of locally connecting conductive layers.
Since in a static random access memory (SRAM) having a full CMOS memory cell, a one unit memory cell is constructed of six MOS transistors, the number of contacts connecting transistors to fabricate a unit memory cell increases more than for other kinds of memory cells. For example, a contact of tungsten (W) matter having a pitch of 0.20 μm should be formed when a high integration semiconductor device has a design rule for an interval under 0.10 μm therefore, but it is actually impossible to obtain a contact patterning of such a size even if the current advanced technique of lithography is used.
Therefore, a method of overcoming the difficulty for the contact patterning and for reducing the number of contacts can be obtained by a local interconnection wire for locally connecting gate electrodes and/or active regions of a semiconductor device.
FIGS. 1a through 1e illustrate sequential processes of forming a local interconnection wire by forming a common aperture for connecting gate electrodes according to one of various conventional techniques related to the local interconnection wire.
Referring first to FIG. 1a, an oxide film 2 and a polysilicon film 3 are sequentially accumulated entirely on a p-type semiconductor substrate 1, and a patterning is then performed through a photolithographic process, to obtain a gate pattern 4 formed on the gate oxide film 2. The gate pattern 4 is used as an ion implantation mask, to implant an n-type impurity ion by a relatively low energy into the semiconductor substrate 1 so as to form a low density source/drain region 6 to then form a gate spacer 7 at the sidewalls. The gate spacer 7 is used as an ion implantation mask, to implant an impurity ion by a relatively high energy into the low density source/drain region 6, so as to form a high density n-type (n+) source/drain region 8 having an impurity of density higher than the low density at a portion of the low density source/drain region 6. The low density source/drain region 6 and the high density source/drain region 8 constitute an LDD (lightly doped drain)-type source/drain region 9 as an active region that is designated by a reference number 9 in the drawing. Subsequently, a refractory metal such as cobalt (Co), etc. is entirely deposited thereon, to be then thermal processed, thus forming a metal silicide film 5 having a resistance value lower than a resistance value of the polysilicon film 3 on an upper part of the gate pattern 4. The gate pattern 4 and the metal silicide film 5 together constitute a gate electrode 13, 14. Then, entirely thereon, an etch stop film 10 is formed, and an insulation film such as a BPSG film, etc. is then deposited overall. This insulation film is well known as an interlayer insulation film 12 in this field since it is positioned between an upper layer and a lower layer thereof to serve an isolation function.
Next, referring to FIG. 1b, a flattening process is executed and a deposition process is then performed to form a hard mask. The flattening process such as a chemical mechanical polishing (CMP) is progressed after the process of FIG. 1a, to flatten the interlayer insulation film 12. Then, a SiN/SiON film 15 is deposited on the interlayer insulation film 12 to become a hard mask. This SiN/SiON film 15 is deposited to increase etching precision of the etching process to be executed in a post process.
With reference to FIG. 1c, a photoresist pattern for exposing an interval (l) between gate electrodes 13, 14 which will be connected with each other, is formed, and next, the interlayer insulation film 12 and the etch stop film 10 in the interval (l) are sequentially etched to expose a surface of the gate electrodes 13, 14, to thus form a common aperture (ha). In this case, the surface of the gate electrodes 13, 14 is formed with a metal silicide film 5, while, the upper part of the active region 9 is formed with the interlayer insulation film 12, thus the upper part of the active region 9 is excessively etched in that sequential etching process. If the interlayer insulation film 12 becomes too thin by the excessive etching, it will be difficult to guarantee a determined thickness margin. That is, a local interconnection layer 16 of FIG. 1d that will to be filled into the common aperture (ha) may be directly contacted with an upper part of the active region 9, forming a short circuit, or short. For example, if the thickness of the polysilicon film 3 is under 1200 Å, shorts can be generated very frequently.
Although the SiN/SiON film 15 was conventionally deposited to be used as the hard mask, it was still very difficult to substantially reduce the occurrence probability of short between the local interconnection layer 16 and the active region 9 caused by excessive etching of the interlayer insulation film 12 formed on the active region 9.
After the process of FIG. 1c, the metal filling process and the flattening process are progressed, hence the local interconnection layer 16 is obtained as shown in FIG. 1d. Describing FIG. 1d more in detail, the metal layer is entirely deposited into the common aperture (ha) to form the local interconnection layer 16, and then a flattening process such as CMP is executed, to thus form the local interconnection layer 16 for connecting the gate electrodes 13, 14.
With reference to FIG. 1e, since the SiN/SiON film 15 as the hard mask is not completely removed by the flattening process, the local interconnection layer 16 is re-etched, which completely removes the remaining SiN/SiON film 15. Then, the surface of the local interconnection layer 16 still having an irregularity is flattened again.
As was described above, according to the prior art of FIGS. 1a through 1e, the etching process of the hard mask composed of the SiN/SiON film, etc. and the flattening process of the local interconnection layer, are required separately by the hard mask forming process, thus there are many process steps. This increases the manufacturing cost for semiconductor devices.
FIGS. 2a through 2d sequentially illustrate processes of forming a common aperture for connecting gate electrodes to produce the local interconnection wire, according to an aspect of the prior art.
The processes until the forming process of the interlayer insulation film are the same as or similar to the description of FIG. 1a, after at least two MOS transistors are formed on a semiconductor substrate, hence, the duplicated description will be omitted from the following and will be described thereafter.
Referring first to FIG. 2a, the flattening process such as CMP, etc. is executed to flatten the interlayer insulation film 12 of an oxide series already formed in the previous process, and the SiN/SiON film 15 which is to become the hard mask is deposited on this interlayer insulation film 12. The SiN/SiON film 15 is then deposited to increase etching precision of the etching process that will be performed in a post process. Subsequently, a photoresist pattern is formed to expose an interval (l1) between the gate electrodes 13, 14 which will be connected with each other and expose a portion (l2) of the active region 11 formed from the outer ends of the gate electrodes 13, 14. Next, the interlayer insulation film 12 and the etch stop film 10 within the interval (l1) are sequentially etched so as to expose the surface of the gate electrodes 13, 14, to thus form the common aperture (ha) and a first recess pattern (hb) of the active region 11. In this case, the surfaces of the gate electrodes 13, 14 are formed with the metal silicide film 5, while, an upper part of the active region 9 is formed with the interlayer insulation film 12, thus the upper part of the active region 9 can be etched excessively in that sequential etching process. If the interlayer insulation film 12 is thinned by the excessive etching, a given thickness margin cannot be guaranteed. That is, it may cause a short where the local interconnection layer 16 of FIG. 1d filled into the common aperture (ha) is directly contacted with the upper part of the active region 9.
With reference to FIG. 2b, the pattern exposing the portion (l2) of the active region 11, namely, the first recess pattern (hb), is formed, and the interlayer insulation film 12 and the etch stop film 10 within the first recess pattern are sequentially etched so as to expose the surface of the active region 11, to thus form a second recess pattern (hc) of the active region 11.
After the process of FIG. 2b, a metal filling process and a flattening process are performed to obtain the local interconnection layer 16 shown in FIG. 2c. Describing FIG. 2c more in detail, a metal layer is entirely deposited to form the local interconnection layer 16 in the common aperture (ha) and in an aperture (hd) of the active region as the first and second recess patterns (hb, hc). Then, a flattening process such as CMP is progressed to form the local interconnection layer 16 for locally connecting between the gate electrodes 13, 14 and between the active regions.
Referring to FIG. 2d, since the SiN/SiON film 15 used as the hard mask is not completely removed by the flattening process, the local interconnection layer 16 is re-etched so as to completely remove the remaining SiN/SiON film 15. After completely removing the remaining SiN/SiON film 15, the process of flattening the surface of the local interconnection layer 16 whose surface is irregular is again performed.
That is, the prior art requires the deposition process of the SiN/SiON film 15 and the specific etching and flattening processes for the removal of the SiN/SiON film 15.
In the following, several problems of the local interconnection wire forming method of the prior art are described.
First, the higher the integration of a memory device is, the more the number of contacts at a given area is increased. In order to solve this problem, a local interconnection wire for locally connecting between gate electrodes and between active regions is formed, but if an interlayer insulation film is thinned by an excessive etching, a determined thickness margin cannot be guaranteed and this brings about a high occurrence probability for a short between a local interconnection layer and an upper part of active region.
Second, in order to prevent this short between the local interconnection layer of gate electrodes and the active region, a SiN/SiON film is deposited before an etching process of the interlayer insulation film, and is then used as a mask, to thus increase precision of the etching process. However, an etching process for the hard mask constructed of the SiN/SiON film, etc. and a flattening process for the local interconnection layer are needed separately due to the hard mask formation process, thus there are a large number of process steps. This increases the manufacturing cost of semiconductor devices.
Embodiments of the invention address these and other limitations in the prior art.